Referring now to FIG. 1, a schematic diagram illustrates the physical layout and architecture of the field programmable gate array (FPGA) circuit discussed in patent application Ser. No. 08/222,138, entitled "TILE BASED ARCHITECTURE FOR FPGA", filed concurrently, in which the present invention may operate. This FPGA comprises logic elements, such as T11 and T12, which may be selectively programmed to implement a wide range of Boolean combinational and sequential operations. The advantage of the FPGA is that a prefabricated generalized circuit can be used to implement relatively complex digital functions without the need for designing and fabricating custom integrated circuits. The logic elements contain memory arrays which are used to store functional state tables. The logic elements connect to exterior pins of the integrated circuit package through bonding pads such as P1 through P10, which surround the periphery of the FPGA. These pads provide input and output signals to the FPGA, and provide a means for connecting power (VCC) and ground (GRID) to the circuit. The logic elements connect to the pads through an interface structure of input/output (I/O) edge cells such as IOI-1 through IOI-5. In the circuit shown in FIG. 1, each edge cell can be programmed to connect to adjacent edge cells and can be manufactured to connect to up to four bonding pads. In FIG. 1, pads P1, P2 and P3 are connected to input/output edge cell IOI-1. Pad P4 is connected to edge cell IOI-2. Because the edge cells are programmably connectable to each other, it is possible to connect any pad to its corresponding edge cell and through the interface structure to any one of a plurality of logic elements interior to the array. The interface structure allows for additional programmable wiring from one pad to another pad or from one logic element to another logic element.
One method of testing an FPGA is by transmitting test vector signals from a chosen pad through the logic elements to be tested to another pad (which thus serves for this purpose as an output pad). The .signals received at the output pad are read and compared to expected results to determine circuit functionality. The cost of testing an FPGA in this manner is potentially fifty percent of the cost of the device. The advent of smaller sized logic circuitry has allowed a greater number of circuit elements to be placed on a single die. However, the size of pads has not changed as dramatically. Thus, the maximum number of pads available on a die has increased only slowly while the number of logic cells in a logic array has greatly increased due to the reduction in size of the components. Electrical testing of dice having reduced sized circuitry is improved by implementing scan chains to sequentially test the increased quantity of logic cells.
In conventional die testing using scan chains, an input pad transmits incoming data to a top or bottom cell in a column of logic cells, which in turn shifts the data to the next cell, and so on through each cell in the column. The data are then output to an output pad and observed. In this configuration, a large number of pads is desirable for testing because the more pads that are available, the more entry ports there are for transmitting the test vector signals into the logic array or exit ports at which to observe the test results. One problem with testing state-of-the-art logic arrays is that the ratio of logic cells to input/output pads is becoming greater, due to the relative reduction in size of the logic circuitry compared to the size of the pads. This size reduction allows a greater number of logic cells to be placed on a single die, without a corresponding increase in the maximum number of pads that can fit on a die. There are fewer pads available for testing a given amount of logic circuitry and thus fewer entry and exit ports for testing.
In addition, FPGAs present a unique testing problem in that the same model of FPGA die can be placed in many different packages with different numbers of pins. In order to maximize testing speed for all packages, it is desirable to apply test signals to all test pins provided in the package. But some adaptation is needed to achieve complete testing when a package is used which has a small number of pins.